Embedded Systems Design I is focused on fully understanding the workings of an 8086 based board. The board has several I/O devices, including a Priority Interrupt Controller (PIC), Programmable Interrupt Timer (PIT), and a Universal Synchronous/Asynchronous Receiver Transmitter (USART). The memory devices included are 16 kB of EEPROM and 2 kB of SRAM.

In ESD I, the labs scale from a basic program that writes data to SRAM in order to test out the memory subsystem up through the final lab which consists of writing a sophisticated monitor program that can be used to test out every feature on the circuit board.

The figure above shows the help file for the monitor program. This screenshot was taken after a few slight modifications were made to the monitor program so that it can be used alongside the DMA Transfer menu designed in ESD II.

In Embedded Systems Design II, a thorough understanding of the existing system is assumed, and the student is challenged to add a DMA Controller and a set of FIFOs to the system to interface to a slow-speed I/O device.

The theory of operations that I wrote for this project includes the basics of DMA Transfers, why they are useful for improving system performance, a block diagram for this system, final memory and I/O maps of the system, a flow chart of the final software solution, and a quick analysis of the improved bus utilization.

Shown above is the menu system that was designed for controlling DMA Transfers. Also shown is the available options for when SRAM is selected as the source of the transfer. These patterns were chosen because they are easy to check for data integrity when viewing the data transfer on the logic analyzer.

Finally, the figure above shows what a DMA Transfer looks like on the system busses and control lines. In this case, the DMA Controller has been programmed to perform 5 transfers from a location in memory that has been written with the "Alternating 0xAAAA w/ 0x5555" pattern (this data can be seen on the line labeled D[15-0]). The FIFO_WRITE# line that is shown is connected to the write signal on the FIFOs, and RD# is the read line connected to the SRAM devices. DREQ is the DMA Request line generated in programmable logic, which is related to the FIFO Full and FIFO Empty flags. DACK is DMA Acknowledge for the channel that the FIFOs are on. HOLD and HLDA are used for arbitration with the processor for bus control. Finally, the FIFO Full and FIFO Empty flags are shown at the bottom of the screen capture.

Embedded Systems Design I and II have taught me a lot about the operation of a simple embedded system, as well as the interoperation of many of the devices common to such a system. In ESD II I learned a lot about debug techniques using a logic analyzer and oscilloscope, as well as several of the common mistakes that a designer is likely to come across on the first rev of a new board.